1. Field of the Invention
The present invention relates to a multilayer wiring technique, and particularly to a multilayer wiring structure which is characterized in the structure of an electrode portion, and a method of manufacturing the same. The multilayer wiring structure of the present invention is applicable to wirings in a semiconductor device, for example.
2. Description of the Related Art
With respect to a semiconductor device, a multilayer wiring structure is formed on the surface of a semiconductor substrate in order to establish the wiring between various types of functional elements constituting the semiconductor device. In the multilayer wiring structure, a plurality of wiring layers are provided through interlayer insulating films, and the wirings of the respective wiring layers are conducted to one another at suitable positions by conductive members (via metal) filled in via holes which are respectively formed in the insulating films.
Recently, higher density wiring has been gradually required, and this requirement has caused increasing tendencies of reducing the thickness of the interlayer insulating films constituting such a multilayer wiring structure as described above. When the thickness of the interlayer insulating film is reduced, parasitic capacity trends to increase. Therefore, material having dielectric constant which is as low as possible is preferably used for the interlayer insulating film. As the interlayer insulating film having a low dielectric constant may be used organic materials such as hydrogen silsesquioxane (HSQ), fluorinated carbon (a-C:F), benzocyclobutene (BCB) or the like. However, the organic interlayer insulating film is generally lower in strength and adhesiveness or adhesion than the inorganic interlayer insulating film made of silicon oxide or silicon nitride for example.
The multilayer wiring structure is provided with an electrode pad serving as an electrode portion for establishing electrical connection with an external circuit, and the electrode pad is generally formed on the uppermost wiring layer. The connection between the electrode pad and the external circuit is performed by wire bonding. In the wire boding process, press force based on ultrasonic vibration to contact the bonding wire to the electrode pad by a bonding head and tensile force at the retraction time of the bonding head are applied to the electrode pad.
Accordingly, in the multilayer wiring structure using organic layer insulating films which are low in strength and adhesiveness, there is a risk that exfoliation occurs between the insulating films, cracks occur in the insulating films or an metal film of the electrode pad is exfoliated from the organic interlayer insulating film through the wire bonding process.
FIGS. 27 to 30 show a method of manufacturing a conventional multilayer wiring structure.
First, as shown in FIG. 27, a first interlayer insulating film 30 is formed on a semiconductor substrate 1 in which various functional elements such as transistors, diodes, capacitors, etc. are formed, and a metal film is formed on the first interlayer insulating film 30 and then subjected to a patterning treatment by using an etching technique to form a metal film pattern 33. As not shown, a wiring of a wiring layer containing the metal film pattern 33 is electrically connected to each of the functional elements of the semiconductor substrate 1 through via metal filled in a via hole which is formed at a suitable position in the first interlayer insulating film 30.
Subsequently, as shown in FIG. 28, an interlayer insulating film is formed on the resultant body of FIG. 27 and then a hole which is slightly smaller than the size of the metal film pattern 33 is formed in the interlayer insulating film, whereby the electrode pad 33 is fixed by second interlayer insulating films 31a, 31b.
Subsequently, as shown in FIG. 29, a metal film is formed on the resultant body of FIG. 28 and then subjected to a patterning treatment by using the etching technique to form a metal film pattern 34. The metal films of the metal film pattern 33 and the metal film pattern 34 are brought into close contact with each other. As not shown, the wirings of the wiring layer containing the metal film pattern 34 are connected to the wirings of the wiring layer containing the metal film pattern 33 through via metal filled in via holes which are formed at suitable positions in the second interlayer insulating films 31a, 31b as occasion demands.
Subsequently, as shown in FIG. 30, an insulating film is formed on the resultant body of FIG. 29 and a hole which is slightly smaller than the size of the metal film pattern 34 is formed, whereby the metal film pattern 34 is fixed by upper insulating films 32a, 32b. Thereafter, a wire 20 is bonded to the metal film pattern 34. The electrode pad is constructed by the metal film patterns 33, 34.
In the multilayer wiring structure thus obtained, the second interlayer insulating films 31a, 31b cover the peripheral portion of the metal film pattern 33, and likewise the upper layer insulating films 32a, 32b cover the peripheral portion of the metal film pattern 34. Accordingly, according to this structure, when organic insulating films having low dielectric constant are used for the second interlayer insulating films 31a, 31b and the upper layer insulating films 32a, 32b, the organic films which are low in film strength and also low in adhesiveness to metal films cover the peripheral portion of the electrode pad, so that cracks are liable to occur in the organic layer insulating films. Further, this structure is not suitable to a multilayer wiring structure having a number of layers because the interlayer insulating films are not flattened.
FIGS. 31 to 37 show another method of manufacturing a conventional multilayer wiring structure.
First, as shown in FIG. 31, a first interlayer insulating film 41 is formed on a semiconductor substrate 1 in which various functional elements such as transistors, diodes, capacitors, etc. are formed, and then first-layer via metal 8 is filled into a via hole formed in the insulating film 41. Further, a metal film is formed on the interlayer insulating film 41 and then subjected to a patterning treatment by using the etching technique to form a first-layer wire 9. The first-layer wire 9 is electrically connected to each of the functional elements of the semiconductor substrate 1 through the first-layer via metal 8. Further, an interlayer insulating film is formed thereon, and flattened to form a second layer insulating film 42. Second-layer via metal 10 is filled into a via hole formed in the second interlayer insulating film 42, and a metal film 46 is formed thereon.
Subsequently, as shown in FIG. 32, the metal film 46 is subjected to a patterning treatment by using the etching technique to form a second-layer wiring 11. At this time, the metal film pattern 5 is formed at the position where the electrode pad will be formed.
Subsequently, as shown in FIG. 33, an interlayer insulating film 43' is formed thereon.
Subsequently, as shown in FIG. 34, the interlayer insulating film 43' is subjected to a chemical/mechanical polishing treatment (CMP) to be flattened, thereby obtaining a third interlayer insulating film 43.
Subsequently, as shown in FIG. 35, a via hole is formed in the third interlayer insulating film 43, and a metal film 47 is deposited thereon, whereby a metal film 48c is filled into the via hole formed at the positions corresponding to the second-layer wiring 11, and also metal films 48a, 48b are filled into via holes formed at the positions corresponding to the metal film pattern 5.
Subsequently, as shown in FIG. 36, the upper surface portion of the metal film 47 is removed by an etch back method, whereby third-layer via metal 12 connected to the second-layer wirings 11 is formed and also via metal 45a, 45b connected to the metal film pattern 5 are formed. Since the upper surface portion of the metal film 47 is removed and flattened by the etch back method to form via metal 45a, 45b as described above, the area of each of the via holes to be filled with the metal films 48a, 48b cannot be increased to the same level as the metal film pattern 5. This is because if the area of the via hole is increased, it is difficult to perfectly fill the metal film 47 into the via hole while flattening the surface of the metal film 47 in the via hole by the etch back method.
Subsequently, as shown in FIG. 37, a metal film is formed and then subjected to the patterning treatment by the etching technique to form a third-layer wiring 13. At this time, a metal film pattern 7 is formed at the position corresponding to the metal film pattern 5. The metal film pattern 7 is connected to the metal film pattern 5 through the via metal 45a, 45b. Further, an interlayer insulating film is formed thereon and then flattened by CMP to form an upper-layer insulting film 44. Subsequently, a passivation film 19 having an opening at the portion corresponding to the electrode pad 7 is formed, and then a wire 20 is bonded to the metal film pattern 7. The electrode pad is constructed by the metal film pattern 7.
In the multilayer wiring structure thus obtained, since the process of etching back the metal film 47 when the via metal 12 is formed as described above, it is difficult to simultaneously flatten the minute via metal 12 and the metal film pattern in the via hole having the area as large as the electrode pad. Therefore, the metal film pattern 5 having the area as large as the electrode pad 7 is formed at the time when the second-layer wiring 11 is formed, and then the electrode pad 7 is formed at the time when the third-layer wiring 13 is formed. The electrode pad 7 and the meal film pattern 5 are connected to each other by the via metal 45a, 45b to enhance the strength to impacts in the wire bonding process.
In this structure, however, when an organic insulating film having low film strength is used as the interlayer insulating film, stress is concentrated to the interlayer insulating film portion sandwiched between the metal film pattern 5 and the metal film pattern (electrode pad) 7, and cracks may occur at this portion with high probability. Therefore, this structure is not sufficient.